AMD has launched its EPYC Venice processor, the first x86 server chip built on TSMC's 2nm process, and the Helios rack-scale AI system at its Advancing AI 2026 conference. The company has secured commitments from major tech giants, including Meta, Microsoft, Oracle, and OpenAI.
TL;DR
- AMD introduces EPYC Venice, the first x86 server processor on TSMC's 2nm process, and the Helios AI system.
- Venice offers significant performance and power efficiency improvements over previous generations.
- Helios integrates Venice CPUs with Instinct MI450-series GPUs, providing a complete AI platform.
What happened
AMD's Advancing AI 2026 conference kicked off with the commercial debut of the EPYC Venice processor and the Helios rack-scale AI system. Venice is the first x86 server processor in volume production on TSMC's 2nm process node, featuring Gate-All-Around (GAA) nanosheet transistors. The Helios system integrates Venice CPUs with Instinct MI450-series GPU accelerators, offering a complete AI platform.
AMD has secured commitments from major tech giants, including Meta, Microsoft, Oracle, and OpenAI, for the Helios system. The company also announced that Venice will be available in standalone CPU servers starting in Q3 2026, with specific configurations and pricing to be revealed later.
Why it matters
The launch of Venice and Helios provides enterprise infrastructure teams with a complete current-generation AI stack, with no comparable response from Intel until mid-2027. This creates a real procurement decision point for teams evaluating server CPUs and AI systems.
Venice's advanced transistor technology and redesigned architecture offer significant performance and power efficiency improvements, making it a compelling option for data centers. The Helios system's integrated platform and open-standard UALink protocol provide a scalable and flexible solution for AI workloads.
Key facts
- Venice is the first x86 server processor in volume production on TSMC's 2nm process node.
- Venice features Gate-All-Around (GAA) nanosheet transistors, offering 10-15% performance improvement or 25-30% power reduction over the previous generation.
- Venice supports 16 DDR5 memory channels, delivering up to 1.6 TB/s of bandwidth per socket.
- Helios integrates 72 MI455X accelerators and EPYC Venice CPUs, delivering 31 TB of aggregate HBM4 memory and 1.4 PB/s of combined bandwidth.
- Helios is rated at 2.9 exaFLOPS of FP4 inference compute and 1.4 exaFLOPS of FP8 training performance.
- AMD has secured commitments from Meta, Microsoft, Oracle, and OpenAI for the Helios system.
- Venice standalone CPU servers are expected to be available in Q3 2026, with specific configurations and pricing to be revealed later.
- Helios is expected to be available for general enterprise procurement in 2027, with hyperscale customers receiving priority in H2 2026.
Context
AMD's launch of Venice and Helios comes at a time when the AI industry is experiencing rapid growth and demand for advanced AI infrastructure. The company's commitment to open standards and partnerships with major tech giants positions it as a strong competitor in the AI hardware market.
The advancements in transistor technology and system integration demonstrated by Venice and Helios highlight the ongoing innovation in AI infrastructure. As the industry continues to evolve, these developments will play a crucial role in enabling more powerful and efficient AI workloads.
